MOSFET UIS and avalanche energy analysis - Power Circuit - Circuit Diagram

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In the datasheet of a power MOSFET, parameters like single-pulse avalanche energy (EAS), avalanche current (IAR), and repetitive pulse avalanche energy (EAR) are typically included. Many electronic engineers overlook these parameters and their impact on the power system during design. Understanding how these parameters influence practical applications and under what conditions they should be considered is crucial. This article aims to address these questions by exploring the operating conditions of power MOSFETs under unclamped inductive switching scenarios.

Defining and Measuring EAS, IAR, and EAR

The avalanche energy of a MOSFET is tied to its thermal performance and operational state. Ultimately, it results in a rise in temperature, which depends on the power level and the thermal characteristics of the silicon package. The thermal response of a power semiconductor to a fast power pulse (around 100-200 microseconds) can be described by Equation 1:

(Equation 1)

Where A represents the silicon wafer's area, and the constant K is related to the thermal properties of the silicon. From equation (1):

(Equation 2)

Here, tav denotes the pulse duration. When measuring avalanche energy at low currents over extended periods, the power dissipated raises the device's temperature, and the failure current is determined by the peak temperature reached. If the device is robust enough to prevent the temperature from exceeding the maximum allowable junction temperature, the measurement can continue. During this process, the junction temperature typically rises from 25°C to TJMAX, with the ambient temperature remaining constant at 25°C, and the current is usually set at 60% of ID. The avalanche voltage VAV is approximately 1.3 times the device’s rated voltage.

Avalanche energy is generally measured under unclamped inductive switching (UIS) conditions. Among these, there are two values: EAS and EAR. EAS is the single-pulse avalanche energy, defining the maximum energy a device can handle in a single avalanche condition; EAR is the repeated pulse avalanche energy. The avalanche energy depends on the inductance value and the initial current value.

Figure 1 shows the EAS measurement circuit and waveform for VDD decoupling. Here, the driving MOSFET is Q1, the MOSFET being tested is DUT, L represents inductance, and D is the freewheeling diode. Both the MOSFET being tested and the driving MOSFET are turned on simultaneously, applying the power supply voltage VDD to the inductor, exciting the inductor, and causing its current to rise linearly. After the conduction time tp, the inductor current reaches its maximum value; subsequently, both the MOSFET being tested and the driving MOSFET are turned off. Because the inductor current cannot change abruptly, at the moment of switching, the original size and direction of the current are maintained, turning on the freewheeling diode D.

Figure 1 EA decoupled EAS measurement diagram

Since there is parasitic capacitance between the DS of the MOSFET, the inductor L and the CDS form a resonant loop when D is turned on, decreasing the inductor current, thereby raising the voltage on CDS until the inductor current reaches zero, and D turns off naturally. The energy stored in L should be entirely transferred to CDS.

If the inductance L is 0.1mH, IAS=10A, and CDS=1nF, theoretically, the voltage VDS would be:

CDSVDS² = LIAS² (3)

VDS = 3100V

This extremely high voltage value seems unrealistic. From the actual waveform, the DS region of the MOSFET behaves like an anti-parallel diode. With the reverse voltage applied across the diode, it enters the reverse operating region. As the voltage VDS of the DS increases, it rises to a clamp voltage close to the corresponding Zener diode, i.e., V(BR)DSS, and VDS remains relatively stable, staying at the V(BR)DSS value, as shown in Figure 1. At this point, the MOSFET operates in the avalanche region, and V(BR)DSS is the avalanche voltage. For a single pulse, the energy applied to the MOSFET is the avalanche energy EAS:

EAS = LIAS²/2 (4)

Additionally, since the avalanche voltage is positively temperature-dependent, when the temperature of some cells within the MOSFET increases, the breakdown voltage also increases. Consequently, cells with lower temperatures automatically balance out, allowing more current to flow and increase the temperature to raise the avalanche voltage. Furthermore, the measured value depends on the avalanche voltage, which varies with rising temperature during demagnetization.

In the previous explanation, there was a question about determining IAS. Once the inductance is set, is it determined by tp? In reality, for a MOSFET device, IAS must first be determined. In the circuit shown in Figure 1, after selecting the inductor, the current is gradually increased until the MOSFET is completely destroyed, and then the current value is divided by 1.2 or 1.3, representing a derating of 70% or 80%. This current value is IAS. Note that once IAS and L are fixed, tp is also determined.

In the past, the circuit diagram and waveform for traditional EAS measurements are shown in Figure 2. Notice that the final VDS voltage does not drop to zero but remains at VDD, meaning some energy is not converted into avalanche energy.

Figure 2 Traditional EAS measurement chart

In the turn-off region, the area of the triangle corresponding to Figure 2(b) represents energy. Regardless of VDD, the demagnetization voltage is VDS, and the actual demagnetization voltage is VDS-VDD, so the avalanche energy is:

(Equation 5)

For some low-voltage devices, VDS-VDD becomes very small, introducing significant errors, thus limiting the use of this measurement circuit in low-voltage devices.

Different companies currently have varying standards for measuring the inductance used. For low-voltage MOSFETs, most companies are starting to use 0.1mH inductors. It is generally observed that if the inductance value is larger, even though the current value of the avalanche decreases, the final measured avalanche energy value increases because the higher inductance slows down the current rise, giving the chip more time to dissipate heat. However, this approach presents problems related to dynamic thermal resistance and heat capacity, which will be discussed later.