Design and Implementation of SOPC for Automatic Voice Recording System (AVRS)

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Abstract : Based on Altera's high-performance Stratix devices, this paper uses SOPC Builder, DSP Builder, Matlab and Simulink to design a new automatic voice recording system (AVRS), which enables simultaneous monitoring of multi-phone calls. Recording can be widely used in departments that require regular voice recording.
Keywords : automatic voice recording system; SOPC; Nios; Stratix

1 Introduction At present, it is becoming more and more common for all industries to record calls on the telephone. For example, government agencies need online recording and monitoring for national security reasons. The security department needs to record and monitor real-time communication of some key monitoring objects. Government departments and important production departments need to record some important orders; financial banks or securities institutions and transactions related to bulk money need to be recorded; and some businesses and service areas use recorded materials as a means of voice recording and quality of service. At present, telephone voice recording devices used in various industries mainly include a tape telephone voice recording device, a PC-based telephone voice recording device, and a FLASH chip-based telephone voice recording device. These telephone voice recording devices cannot meet the special needs of some users in practical applications due to the disadvantages such as excessive volume or short recording time. Therefore, a voice recording device with large storage capacity, reliable performance and small size is needed.

In response to this situation, we have developed a new type of automatic voice recording system (AVRS), which can monitor and record the conversations of multiple telephones, convert the contents of the call into digital information, and store them on the hard disk in the form of voice files. It can be queried by telephone search method, and the queried voice files can be directly broadcasted by telephone. The system adopts FPGA and large-capacity notebook hard disk, which has high integration degree and large storage information, and information can be stored in the hard disk for a long time, and the document management is convenient and the confidentiality is strong.

2 system structure and function

The application structure of the Automatic Voice Recording System (AVRS) is shown in Figure 1. It is usually composed of a PSTN, a switch, an automatic voice recording system, a computer, and a telephone. The Automatic Voice Recording System (AVRS) designed in this paper has the following functions:
(1) Provides a high-density solution for recording calls of up to 4 to 64 channels in an extension and line mode, supporting ADPCM, G.711, and G.729 compression formats, and is compatible with mainstream switches in the world.
(2) It can provide real-time recording of multi-channel conversations; provide various recording activation methods, such as off-hook control, connection call control or voice control; the operator can start the monitoring function at any time; real-time monitoring of both parties and call quality No effect.
(3) Recording of call information can realize synchronous recording of call information while recording a call voice file, and provide complete call information record, including calling number, called number, call direction, talk time, and call duration.
(4) It can realize the function of remote monitoring and management. It can remotely dial in through the reserved telephone, and can monitor the running status of all channels in real time under voice guidance; it can be based on multiple query conditions (by channel, date and time, calling number, Called number, etc.) Query or delete recordings; can achieve more than 80,000 channels of online storage. Recordings can be stored on the hard disk in the Automatic Voice Recording System (AVRS) and transmitted via the USB port on the device. Go to the computer.

3 hardware design automatic voice recording system by Stratix EP1S125, Nios soft core processor, SDRAM, IDE interface notebook hard disk, PCM codec circuit, configuration device MAX7128S, LCD display module, keyboard, clock circuit, USB interface circuit, telephone line interface circuit And the power supply and other components, the circuit block diagram shown in Figure 2.

3.1 Stratix FPGA
Modern high-capacity, high-speed FPGAs are typically embedded with configurable DSP blocks such as high-speed RAM, PLL, LVDS, and hardware multiply accumulators. FPGAs for digital signal processing can solve parallelism and speed problems well. Its flexible configurability makes the DSP system of FPGAs very easy to modify, easy to test and hardware upgrades.

Altera introduced a new generation of Stratix FPGAs in 2002. It is fabricated in a 0.13 micron and copper process with a 1.5V core voltage. The DSP blocks in Stratix devices provide data processing power higher than DSP processors and are more flexible and economical. Each Stratix DSP module provides up to eight parallel multipliers running at 250MHz with data throughput up to 2GMACS. The largest Stratix device, the EP1S125, consists of 28 DSP blocks that can perform up to 224 parallel multiply operations and provide 56GMACS bus data throughput. Traditional DSP processors can only perform up to 8 simultaneous multiply operations simultaneously, and data throughput is also available. Only 8.8GMACS. In addition to dedicated multipliers in the DSP block, multipliers and DSP functions can be implemented using logic elements (LEs). For example, a 256-order FIR filter can be implemented in a Stratix device with approximately 9600 logic cells. The EP1S120 of the Stratix series includes approximately 114,140 logic cells and can accommodate 11 such filters. Each filter can run at 200MHz, which means that the total throughput of the 563GMACS device can be provided by using LE. Combined with the 56GMACS data throughput provided by the DSP block, Stratix devices provide up to 620 GMACS of total data throughput, so Stratix devices are suitable for large data volume digital signal processing [1].

The system is designed with the Stratix EP1S125, which enables real-time monitoring, recording and storage of multi-channel calls.

3.2 Nios Soft Core Processor The Nios soft core processor is a pipelined, single instruction stream 32-bit RISC embedded processor with performance exceeding 200 DMIPS. It is optimized for the design of Altera's programmable logic devices and on-chip programmable systems. As a configurable general-purpose RISC processor, it can be combined with user-defined logic to form an SOC system and downloaded to Altera's programmable devices. The 32-bit Nios soft-core processor combines external flash memory with large-capacity memory to form a powerful 32-bit embedded processor system with most of the instructions in one clock cycle. The Nios soft core processor family includes both 32-bit and 16-bit versions of the architecture.

3.3 PCM codec circuit The PCM codec circuit in this system design uses IDT821064 codec chip, which provides 4 independent analog audio channels, suitable for enterprise and carrier-class network, wireless network and access network market. The communication device has perfect programmability without external components. The number of channels required for recording according to the needs can be satisfied by adding the corresponding IDT821064. IDT821064 can perform impedance matching, tone generation, hybrid coil balance response correction and gain setting. The appropriate microprocessor interface (MPI) or universal communication interface (GCI) can be selected according to the system structure. It is packaged in a 64-pin PQFP package [2] ].

In the design, the Nios soft core needs to provide GCI interface control signals for each IDT821064. Generally, only one or two transmission commands are sent, no need to occupy too many resources, and in order to facilitate debugging, PIO can be independently operated, through software. They are set and reset to send control commands.

Figure 3 is a timing diagram of the GCI interface. DCL is the data clock signal, FSC is the frame sync signal, and DD/DU is the data output/input signal. According to this timing diagram, we can write relevant HDL code to realize the reception and transmission of PCM serial data.

3.4 IDE Hard Disk Control The IDE interface hard disk drive provides two data transfer modes: PIO mode and DMA mode. Since the PIO mode control is relatively easy, a fast transfer method of programming control input and output is provided. This mode uses high-speed data block I/O, in batches, and uses the interrupt request method to exchange bulk data with the CPU. In the sector read and write operations, the transfer is performed by the internal high-speed PIO data register at a time of 16 bits. Normally, data transmission is in units of sectors, and an interrupt is generated for each sector of data transmitted.

If the CPU wants to write data to the hard disk, first the CPU writes the necessary parameters to the corresponding address register, waits for DRDY to be valid, then writes the opcode to the command register, and the driver sets the DRQ bit of the status register, indicating that it is ready to receive data. The CPU writes the data to the sector buffer through the data register. When the sector buffer is filled, the driver clears the DRQ bit and sets BSY. The driver writes the data in the sector buffer to the disk. When the write is over, the BSY bit is cleared, and the interrupt request signal INTRQ is sent. After receiving the interrupt signal, the CPU reads the driver status register and clears the interrupt signal INTRQ.

If the CPU wants to read data from the hard disk, first write the parameters to the address register and the property register (if needed), then write the command code to the command register, and the command begins execution. At this time, the drive sets BSY=1 in the status register, and simultaneously sends the data in the specified sector on the hard disk to the sector buffer. When the sector buffer is ready for data, set DRQ, clear BSY, and send interrupt request signal INTRQ. After the CPU detects the interrupt, it reads the status register and tests the ERR bit. If it is equal to 1, it goes to error processing. Otherwise, if the DRQ bit is 1, the CPU reads the data from the sector buffer. After the data is read, the driver resets the DRQ. Bit, then the drive resets the BSY bit [3].

4 software design
The software design includes configuration generation SOPC system, transplantation of embedded operating system, design of speech compression algorithm, application level code writing and debugging. A brief introduction is given below.

4.1 Configuration Generation SOPC System SOPC is a combination of SoC technology and programmable logic technology. It is a special embedded system. First of all, it is SoC, which can complete the main logic function of the whole system by a single chip. Secondly, it is a programmable system with flexible design, can be reduced, scalable, upgradeable, and has certain system programmable functions. SOPC design technology covers the entire content of embedded system design technology, including: processor and real-time multitasking operating system (RTOS)-centric software design technology, high-speed circuit design technology based on PCB and signal analysis, hardware and software Collaborative design techniques.

The Automatic Voice Recording System (AVRS) designed in this paper is based on SOPC based on Stratix device EP1S125. In Quartus II, we use SOPC Builder tool to configure and generate system-on-chip. SOPC Builder is a powerful graphical interface-based system definition and customization tool that can be customized in a short time. Depending on the needs of the application, select the IP module, memory, peripheral interface and processor from the SOPC Builder library and configure to generate a highly integrated embedded system.

When configuring the system-on-chip, SOPC Builder automatically generates the necessary arbitration logic to coordinate the work of the various components in the system. We first set the operating frequency of the system to 50MHz. According to the hardware requirements of the system, we can get the system configuration diagram shown in Figure 4. Compile and generate many files including C/C++ language header files and peripheral interface drivers by SOPC Builder. Facilitate the development of subsequent application software.

4.2 μC/OS-II Operating System Migration μC/OS-II is a real-time operating system with open source code, compact structure and deprived real-time kernel. Its core provides tasks scheduling and management, time management, synchronization and communication between tasks, memory management and interrupt services. μC/OS-II is suitable for small control systems. It has high performance, small footprint, good real-time performance and strong scalability. It is stable and reliable, and has been widely used in aviation, medical equipment and industrial control. And other fields [4].

μC/OS-II is designed with full consideration of the need to shift values ​​on different platforms. The platform-related parts are limited to a small range. For the different platforms, only the following functions and macros need to be rewritten.

OS_ENTER_CRITICAL and OS_ENTER_CRITICAL: These are two macros for critical section protection. This is done using the assembly code off interrupt in this design.

OS_TASK_SW: This is a macro for task switching. In this design, the CPU is implemented by the software interrupt mode, that is, the macro is called to generate a software interrupt, and then the corresponding interrupt handler is used to implement the task context protection and task switching.
OSIntCtxSw: implements interrupt-level task switching, implemented in pure assembly.
OSCtxSw: Implements user-level context switching, implemented in pure assembly.
OSTickISR: A handler for the system timer interrupt, implemented in pure assembly.
OSTaskStkInit: Used to initialize the task stack when creating a task.

4.3 Design of Speech Compression Algorithm The design of speech compression algorithm is based on tools such as DSP Builder, Matlab and Simulink. DSP Builder is a system-level tool developed by Altera Corporation for DSP development. It appeared as a Simulink toolbox from Matlab. Matlab is a powerful mathematical analysis tool widely used in scientific computing and engineering calculations. It can perform modeling, parameter estimation and performance analysis of complex digital signal processing systems. Simulink is an integral part of Matlab for graphical modeling simulation.

In the design, we first use Matlab's powerful system design, analysis capabilities and modules (or IP cores) provided by DSP Builder to complete the top-level system design and system simulation test, realize ADPCM, G.729 compression algorithm, and verify the speech compression algorithm. The correctness is then automatically converted into VHDL RTL representation and tool command language (TCL) script by Signal Compiler in DSP Builder, and then RTL level function simulation, combined with QuartusII software for integration, adaptation and Timing simulation.

4.4 Application-Level Code Writing and Debugging VHDL code is written in Quartus II to control various parts of the system. Finally, functional simulation of RTL level is performed, and synthesis, adaptation and timing simulation are performed. The set embedded logic analyzer Signal Tap II can be adapted and downloaded to the FPGA chip before forming the SOF file for programming the specified FPGA, and then can be observed through the JTAG port through the Simulink window of Matlab. The real-time working waveform of the DSP hardware module in the chip measured by Signal TapII enables hardware simulation and debugging.

5 Conclusion
The most prominent feature of the Automatic Voice Recording System (AVRS) designed in this paper is that the design using FPGA and SOPC technology is quite fast. Due to the complete functionality of the SOPC development environment, attention can be focused on the overall architecture and functionality of the system without the need to consider the detailed circuit design too much, while also achieving better system stability and reliability.

The Automatic Voice Recording System (AVRS) has undergone preliminary simulation tests to achieve very good practical results, which can meet financial, insurance, electricity,